The uses of VCXO's are well known. They are particularly useful, for example, in phase lock loop (PLL) applications for supplying a variable frequency output signal to the loop phase detector under the control of the loop filter for locking the output of the VCXO to the frequency (or a multiple thereof) of an input signal applied to the phase detector. Other uses are also quite well known.
FIG. 1 is an example of a conventional (prior art) VCXO of the Pierce type and comprises an inverting logic gate U1 provided with a DC feedback path (feedback resistor Rf) for biasing the inverter U1 to a linear operating region and an AC feedback path for causing oscillations to occur and for controlling the frequency of the oscillations in response to a frequency control signal, Vbias, applied to a control input terminal T2.
The AC feedback path 20 includes a source resistor Rx that is AC coupled via a capacitor C1 to a first plate of a crystal X1 and is coupled to ground via a first varactor tuning diode D1. The second plate 24 of crystal X1 is coupled by a second varactor diode D2 to ground and to the input 1 of the inverter U1 via a DC blocking capacitor Cb. A bias voltage, Vbias, provided at an input terminal T2 via a suitable source (not shown), is coupled via resistors R1 and R2 to varactor diodes D1 and D2, respectively, for tuning the VCXO. The output 2 of inverter U1 is coupled to an output terminal T1 for supplying a clock output signal CL to external utilization circuitry (not shown). For purposes of illustration and explanation, exemplary element values are shown in the prior art example of FIG. 1.
In operation, the feedback resistor Rf provides DC bias for biasing inverter U1 to a linear operating region as previously noted. In the AC feedback path 20, the crystal X1 and the two varactor diodes D1 and D2 form a so-called "tank" circuit that determines and controls the oscillator frequency. As the control voltage (Vbias) at input terminal T2 increases, the capacitance of the varactor diodes D1 and D2 decreases thereby increasing the frequency of the VCXO output clock signal CL at teminal T1. Conversely, a decrease in Vbias will decrease the frequency of the output clock signal, CL.